--
-- VHDL Architecture Balance.Balance_module.arch
--
-- Created:
--          by - toban963.student (southfork-05.edu.isy.liu.se)
--          at - 10:56:26 09/29/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY balance IS
   PORT( 
      fpga_clk        : IN     std_logic;
      fpga_reset_n    : IN     std_logic;
      --Audio_in_right  : IN     std_logic_vector (3 DOWNTO 0);
      --Audio_in_left   : IN     std_logic_vector (3 DOWNTO 0);
     -- Volume_control  : IN     std_logic_vector (15 DOWNTO 0);
      --Audio_out_right : OUT     std_logic_vector (3 DOWNTO 0);
      --Audio_out_left  : OUT     std_logic_vector (3 DOWNTO 0); 
      current_balance : BUFFER integer range 0 to 10;
      balance_in      : in std_logic_vector ( 1 DOWNTO 0 )      
   );

-- Declarations

END balance ;

--
ARCHITECTURE arch OF balance IS
SIGNAL aud_reg_right : std_logic_vector(23 DOWNTO 0);
SIGNAL aud_reg_left  : std_logic_vector(23 DOWNTO 0);
BEGIN
  
  PROCESS(fpga_clk)
  BEGIN
      if fpga_reset_n = '0' then
          current_balance <= 5;
      elsif rising_edge(fpga_clk) then
        IF balance_in = "11" THEN
          IF current_balance < 10 THEN
           current_balance <= current_balance + 1;
          END IF;
        ELSIF balance_in = "01" THEN
          IF current_balance > 0 THEN
            current_balance <= current_balance - 1;
          END IF;
        END IF;
      end if;
    END PROCESS;
    
  --  aud_reg_right <= Audio_in_right;
   -- aud_reg_left <= Audio_in_left;
    
       
 -- PROCESS(fpga_clk)
  --  BEGIN   
      
 --   if rising_edge(fpga_clk) then
 --     CASE current_balance IS
 --     WHEN 0 => audio_out_right <= "0000000000" & Audio_reg_right(23 downto 10);
 --                   audio_out_left <= Audio_reg_left(23 downto 0);
 --                   
 --    WHEN 1 => audio_out_right <= "000000000" & Audio_reg_right(23 downto 9);
  --                  audio_out_left <= "0" & Audio_reg_left(23 downto 1);
--                    
--      WHEN 2 => audio_out_right <= "00000000" & Audio_reg_right(23 downto 8);
--                     audio_out_left <= "00" & Audio_reg_left(23 downto 2);
--                     
--      WHEN 3 => audio_out_right <= "0000000" & Audio_reg_right(23 downto 7);
--                     audio_out_left <= "000" & Audio_reg_left(23 downto 3);   
--                    
--      WHEN 4 => audio_out_right <= "000000" & Audio_reg_right(23 downto 6);
--                     audio_out_left <= "0000" & Audio_reg_left(23 downto 4);
--                     
--      WHEN 5 => audio_out_right <= "00000" & Audio_reg_right(23 downto 5);--5
--                      audio_out_left <= "00000" & Audio_reg_left(23 downto 5); --5
--                      
--      WHEN 6 => audio_out_right <= "0000" & Audio_reg_right(23 downto 4);
--                      audio_out_left <= "000000" & Audio_reg_left(23 downto 6);
--                      
--      WHEN 7 => audio_out_right <= "000" & Audio_reg_right(23 downto 3);
--                      audio_out_left <= "0000000" & Audio_reg_left(23 downto 7);
--                      
--      WHEN 8 => audio_out_right <= "00" & Audio_reg_right(23 downto 2);
--                      audio_out_left <= "00000000" & Audio_reg_left(23 downto 8);
--                      
--      WHEN 9 => audio_out_right <= "0" & Audio_reg_right(23 downto 1);
--                      audio_out_left <= "000000000" & Audio_reg_left(23 downto 9);
--                      
--      WHEN 10 => audio_out_right <= Audio_reg_right(23 downto 0);
--                      audio_out_left <= "0000000000" & Audio_reg_left(23 downto 10);
--end case;
--end if;
--end process;
  
END ARCHITECTURE arch;

